2. Description of Related Art
Generally, bus transactions in computer systems involve a "master" and a "target". The master is the bus agent that initiates the transaction, and the target is the bus agent that responds to or is selected by the transaction. If the bus protocol requires a determination of which agent is the target of a particular transaction, that determination can be centralized or distributed. When target determination is distributed, the target itself is responsible for claiming the transaction.
The protocol of the Peripheral Component Interconnect (PCI) bus includes distributed target determination (PCI Local Bus Specification, Revision 2.1, published July 1995). Bus masters initiate transactions by asserting the FRAME# signal and driving the address of the transactions onto AD lines. Normally, each transaction has one target, so one and only one agent on the bus has a responsibility to respond to the transaction as the target. That agent claims the responsibility to respond to the transaction by asserting the DEVSEL# signal. The responsibility to respond to the transaction includes a responsibility to assert the TRDY# signal to indicate that the target is ready to complete the transaction and either a responsibility to provide or accept data, depending on whether the transaction is a read or a write.
To determine which agent should claim a transaction, potential target agents decode the address to determine if they are the actual target. Potential target agents that perform such a decode operation are commonly referred to as "positive" decode agents. Assuming that no two targets reside at the same address, no more than one positive decode agent will claim the transaction. By limiting the amount of time available for address decoding, the PCI bus protocol allows a potential target agent to claim transactions without performing a decode by claiming any transaction that is not claimed by a positive decode agent after a finite period of time. Such an agent is commonly referred to as a "subtractive" decode agent. To prevent target conflicts, the prior art allows only one agent on the bus to implement a subtractive decode.
This limitation, which prevents the use of multiple subtractive decode agents on a bus, presents a problem in a system with multiple PCI buses. For example, FIG. 1 shows a system with PCI bus 101 and PCI bus 102 connected by PCI bridge 103. Bridge 103 transfers signals between buses with a delay of two clock periods. Agent 104 resides on bus 101, and is a positive decode agent requiring two clock periods for decoding. Agents 105, 106, and 107 reside on bus 102. Agent 105 is the slowest positive decode agent on bus 102, requiring three clock periods for decoding. Therefore, when agent 105 is targeted, it will claim the transaction on the third clock after the transaction is initiated. Agent 106 is the subtractive decode agent of bus 102, claiming all unclaimed transactions on the fourth clock after initiation of the transaction.
Referring to the timing diagram of FIG. 2 along with FIG. 1, assume that at time 201 agent 107 initiates a transaction that targets agent 104. Due to the delay across bridge 103, the address of the transaction is driven on bus 101 two clock periods after the address is driven on bus 102. Therefore, agent 104 begins decode at time 203, two clock periods after the transaction is initiated. Agent 104 completes decode at time 205, four clock periods after the transaction is initiated, and asserts the DEVSEL# signal on bus 101 to claim the transaction. The DEVSEL# signal is transferred across bridge 103, resulting in the assertion of the DEVSEL# signal on bus 102 at time 207. However, agent 106 will have already mistakenly claimed the transaction at time 205, four clock periods after the transaction was initiated.
One possible solution to this problem might be to increase the finite time period allowed for positive decode. However, that solution would violate the bus protocol, which allows only three clock periods for positive decode, as well as decrease performance by increasing the latency of transactions to the subtractive decode agent. Another possible solution might involve reducing the delay across bridge 103 and restricting the decode time of all agents on bus 101. However, that solution would require performance improvements to bridge 103 and certain agents on bus 101, and decrease flexibility of bus 101 by excluding slow decode agents. Another possible solution might be to require bridge 103 to act as a positive decode agent on bus 102 on behalf of all agents on bus 101. However, that solution would add complexity to bridge 103, as well as decrease flexibility of bus 101 by limiting the available address space and device configuration model to that which can be accommodated by bridge 103.
The present invention overcomes the problems of the prior art described above by providing support for two subtractive decode agents on the same bus in a computer system.